Method for manufacturing cmos structure

ABSTRACT

The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type. In such a process, over doping is used for reducing the number of masks. A doping concentration of a well region may be modified to adjust work function.

CLAIM OF PRIORITY

This application claims priority to Chinese Application No.201410392572.9, filed Aug. 11, 2014 (not published), and claims priorityto Chinese Application No. 201410456374.4, filed Sep. 9, 2014 (publishedas CN 104167391 A), both of which are hereby incorporated by reference.

BACKGROUND OF THE DISCLOSURE

1. Field of the Disclosure

The present disclosure relates to semiconductor technology, and moreparticularly, to a method for manufacturing a complementary metal oxidesemiconductor (CMOS) structure.

2. Description of the Related Art

A CMOS structure includes metal-oxide-semiconductor field-effecttransistors (MOSFETs) of two opposite types (i.e. N-type and P-type) onone semiconductor substrate. The CMOS structure is widely used invarious logical circuits which operates at low power consumption. Acontrol chip of a power converter has advantages of low powerconsumption, high integration level, and high speed, if being on thebasis of a CMOS structure.

To complete a CMOS structure, a well region is typically formed in asemiconductor substrate for at least one type of MOSFET. Source/drainregions of the at least one type of MOSFET are then formed in the wellregion by ion implantation. The well region has a doping type oppositeto that of the MOSFET to be formed therein, and functions as an actualsemiconductor substrate of such a MOSFET. Lightly-doped drain (LDDregion) regions may also be formed between the source/drain regions anda channel region for improving electric field distribution in thechannel region and suppressing a short-channel effect.

In a conventional CMOS process, doping processes are usually independentof each other for different types of MOSFETs. When doped regions of onetype of MOSFETs are formed, active regions of the other type of MOSFETsare blocked, or vice versa. Consequently, a large number of masks mustbe used in various doping steps in the conventional CMOS process, whichincreases manufacturing cost, and may cause low yield and poorreliability of the product due to possible mismatching of differentmasks.

Thus, it is desirable to further reduce manufacturing cost of a CMOSprocess and reduce reliability problem due to the process complexity.

BRIEF DESCRIPTION OF THE DISCLOSURE

In view of this, the present disclosure provides a method formanufacturing a CMOS structure in which less masks are used.

In an embodiment, there is provided a method for manufacturing a CMOSstructure, comprising: forming a first gate stack on a semiconductorsubstrate in a first region; forming a second gate stack on thesemiconductor substrate in a second region; implanting a dopant of afirst type with the first gate stack and the second gate stack as a hardmask, to form a lightly-doped drain region of the first type; andimplanting a dopant of a second type by using a first mask and with thesecond gate stack as a hard mask, to form a lightly-doped drain regionof the second type, wherein the first mask blocks the first region andexposes the second region, wherein when the lightly-doped drain regionof the second type is formed, the dopant of the second type over dopes apredetermined region of the lightly-doped drain region of the firsttype.

Preferably, each of the first gate stack and the second gate stackcomprises a gate conductor and a gate dielectric, and the gatedielectric is disposed between the gate conductor and the semiconductorsubstrate.

Preferably, the gate conductor is made of polysilicon.

Preferably, after the steps of forming the first gate stack and formingthe second gate stack, the method further comprises doping the gateconductor of at least one of the first gate stack and the second gatestack to adjust work function.

Preferably, before the step of forming the first gate stack, the methodfurther comprises at least one of: forming a first well region of thesecond type by implanting a dopant of the second type in the firstregion of the semiconductor substrate; and forming a second well regionof the first type by implanting the dopant of the first type in thesecond region of the semiconductor substrate.

Preferably, at least one of the first well region and the second wellregion has a doping concentration which is controlled in view of athreshold voltage.

Preferably, before the step of forming the first gate stack, the methodfurther comprises forming shallow trench isolation in the semiconductorsubstrate for defining the first region for MOSFETs of the first typeand the second region for MOSFETs of the second type.

Preferably, after the steps of forming the first gate stack and formingthe second gate stack, and before the steps of forming the lightly-dopeddrain region of the first type and forming the lightly-doped drainregion of the second type, the method further comprises forming gatespacers on side walls of the first gate stack and the second gate stack.

Preferably, after the steps of forming the lightly-doped drain region ofthe first type and forming the lightly-doped drain region of the secondtype, the method further comprises forming gate spacers on side walls ofthe first gate stack and the second gate stack.

Preferably, after the steps of forming the first gate stack and formingthe second gate stack, and after the step of forming the lightly-dopeddrain region of the first type, and before the step of forming thelightly-doped drain region of the second type, the method furthercomprises forming gate spacers on side walls of the first gate stack andthe second gate stack.

Preferably, the method further comprises implanting a dopant of thefirst type by using a second mask and with the first gate stack and thegate spacers as a hard mask, to form source/drain regions of the firsttype, wherein the second mask blocks the second region and exposes thefirst region; and implanting a dopant of the second type by using athird mask and with the second gate stack and the gate spacers as a hardmask, to form source/drain regions of the second type, wherein the thirdmask blocks the first region and exposes the second region.

Preferably, the method further comprises implanting a dopant of thesecond type by using the first mask and with the second gate stack andthe gate spacers as a hard mask, to form the lightly-doped drain regionof the second type and source/drain regions of the second type, whereinthe first mask blocks the first region and exposes the second region,and implanting a dopant of the first type by using a second mask andwith the first gate stack and the gate spacers as a hard mask, to formsource/drain regions of the first type, wherein the second mask blocksthe second region and exposes the first region.

Preferably, the method further comprises implanting a dopant of thesecond type by angled ion implantation through the gate spacers to formthe lightly-doped drain region of the second type.

Preferably, after the steps of forming the source/drain regions of thefirst type and forming the source/drain regions of the second type, themethod further comprises performing silicidation to form a metalsilicide layer on the source/drain regions of the first type, on thesource/drain regions of the second type, and on the gate stack.

Preferably, the gate conductor of the first gate stack contains a dopantof the first type, and the gate conductor of the second gate stackcontains a dopant of the first type and a dopant of the second type.

In the present method, a predetermined region of the lightly-dopedregion of the first type is over doped and compensated to be alightly-doped drain region of the second type. Only one mask is used forboth the first-type MOSFETs and second-type MOSFETs when forming thelightly-doped regions, which reduces the number of the masks.Accordingly, the failure of the CMOS structure due to mismatching ofdifferent masks is avoided.

In a preferable embodiment, a doping concentration of the well regionmay be well controlled in view of a threshold voltage when at least oneof the first well region and the second well region is formed, so thatwork function difference between the gate conductor and the channelregion fulfills design requirements. Thus, an additional ionimplantation for adjusting work function by doping the gate conductor isomitted.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will become more fully understood from the detaileddescription given hereinbelow in connection with the appended drawings,and wherein:

FIGS. 1 to 12 are cross-sectional views showing various stages of amethod for manufacturing a CMOS structure according to an embodiment ofthe present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE DISCLOSURE

Exemplary embodiments of the present disclosure will be described inmore details below with reference to the accompanying drawings. In thedrawings, like reference numerals denote like members. The figures arenot drawn to scale, for the sake of clarity. Moreover, some well-knownparts may not be shown. For simplicity, the structure of thesemiconductor device having been subject to several relevant processsteps may be shown in one figure.

It should be understood that when one layer or region is referred to asbeing “above” or “on” another layer or region in the description ofdevice structure, it can be directly above or on the other layer orregion, or other layers or regions may be intervened therebetween.Moreover, if the device in the figures is turned over, the layer orregion will be “under” or “below” the other layer or region.

In contrast, when one layer is referred to as being “directly on” or “onand adjacent to” or “adjoin” another layer or region, there are notintervening layers or regions present. In the present application, whenone region is referred to as being “directly in”, it can be directly inanother region and adjoins the another region, but not in a dopingregion of the another region.

In the present application, the term “semiconductor structure” meansgenerally the whole semiconductor structure formed at each step of themethod for manufacturing the semiconductor device, including all of thelayers and regions having been formed. The term “source/drain region”means at least one of a source region and a drain region of a MOSFET.

Some particular details of the present disclosure will be describedbelow, such as exemplary semiconductor structures, materials,dimensions, process steps and technologies of the semiconductor device,for better understanding of the present disclosure. However, it can beunderstood by one skilled person in the art that these details are notalways essential for but can be varied in a specific implementation ofthe disclosure.

Unless the context clearly indicates otherwise, each part of thesemiconductor device can be made of material(s) well known to oneskilled person in the art. The semiconductor material includes forexample group III-V semiconductor, such as GaAs, InP, GaN, and SiC, andgroup IV semiconductor, such as Si, and Ge. A gate conductor may be madeof any conductive material, such as metal, doped polysilicon, and astack of metal and doped polysilicon, among others. For example, thegate conductor may be made of one selected from a group consisting ofTaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si,Pt, Ru, W, and their combinations. A gate dielectric may be made of SiO2or any material having dielectric constant larger than that of SiO2. Forexample, the gate dielectric may be made of one selected from a groupconsisting of oxides, nitrides, oxynitrides, silicates, aluminates, andtitanates. Moreover, the gate dielectric can be made of those developedin the future, besides the above known materials.

The disclosure can be embodied in various forms, some of which will bedescribed below.

Referring to FIGS. 1 to 12, various stages of a method for manufacturinga CMOS structure according to an embodiment of the present disclosurewill be described hereinbelow.

As shown in FIG. 1, shallow trench isolations (STIs) 102 are formed in asemiconductor substrate 101. The shallow trench isolations 102 are usedfor defining various active regions of the CMOS structure. In anexample, the semiconductor substrate 101 is a single-crystal siliconsubstrate.

In a preferable embodiment, a photoresist layer is formed on a surfaceof the semiconductor substrate, and then patterned by lithography to bea photoresist mask which exposes those regions other than active regions(also being referred to as field regions). Portions of the semiconductorsubstrate 101 are removed by a conventional etching process which isperformed from top to bottom through openings in the photoresist mask toform shallow trenches. The etching may be dry etching such as ion beammilling, plasma etching, reactive ion etching, laser ablation and thelike, or wet etching using a selective solution of etchant. Then, thephotoresist mask is removed by ashing or dissolution with a solvent.

An insulating layer is then formed on a surface of the semiconductorstructure by a conventional deposition process. The insulating layer hasa thickness at least large enough to fill up the shallow trenches. Forexample, the deposition process may be one selected from a groupconsisting of electron beam evaporation (EBM), chemical vapor deposition(CVD), atomic layer deposition (ALD), and sputtering. For example, asurface of the semiconductor structure may be planarized by chemicalmechanical polishing so that portions of the insulating layer outsidethe shallow trenches are removed and the remaining portions of theinsulating layer form shallow trench isolation(STI).

Next, a photoresist layer is formed on a surface of the semiconductorstructure, and then patterned by lithography to be a photoresist maskPR1 which exposes an active region of a P-type MOSFET. A first ionimplantation is performed by a conventional ion implantation anddriving-in process to form an N-type well region 110 of a P-type MOSFETin the semiconductor substrate 101, as shown in FIG. 2. A dopant reachesthe semiconductor substrate 101 through the openings in the photoresistmask PR1 in the ion implantation. Then, the photoresist mask is removedby ashing or dissolution with a solvent.

An N-type semiconductor layer or region may be formed by implanting anN-type dopant such as P or As in the semiconductor layer or region. Bycontrolling implantation parameters, such as implantation energy anddosage, the dopant may reach a predetermined depth and may have apredetermined doping concentration.

Next, a photoresist layer is formed on a surface of the semiconductorstructure, and then patterned by lithography to be a photoresist maskPR2 which exposes an active region of an N-type MOSFET. A second ionimplantation is performed by a conventional ion implantation anddriving-in process to form a P-type well region 120 of an N-type MOSFETin the semiconductor substrate 101, as shown in FIG. 3. A dopant reachesthe semiconductor substrate 101 through the openings in the photoresistmask PR2 in the ion implantation. Then, the photoresist mask is removedby ashing or dissolution with a solvent.

A P-type semiconductor layer or region may be formed by implanting aP-type dopant such as B in the semiconductor layer or region. Bycontrolling implantation parameters, such as implantation energy anddosage, the dopant may reach a predetermined depth and may have apredetermined doping concentration.

It is well known that a threshold voltage of a MOSFET is mainlydetermined by work function difference between the gate conductor andthe channel region. In a conventional CMOS process, a gate conductor ofan N-type MOSFET is typically doped to adjust its work function, whichfurther changes the threshold voltage. Doping the gate conductor must beperformed in an additional ion implantation process.

In a preferable embodiment, a doping concentration of a P-type wellregion 120 may be well controlled in view of a threshold voltage whenthe P-type well region 120 is formed, so that work function differencebetween the gate conductor and the channel region fulfills designrequirements. In an example, the P-type well region 120 has a dopingconcentration of about 2×10¹⁷/cm³, which is smaller than a typicaldoping concentration of about 7×10¹⁷/cm³ of the P-type well region in aconventional CMOS process. In this preferable embodiment, an additionalion implantation for doping the gate conductor and for adjusting workfunction can be omitted.

In the first ion implantation and the second ion implantation, theN-type well region 110 and the P-type well region 120 are definedrespectively by the photoresist masks. The photoresist masks may bedesigned to have predetermined patterns so that the N-type well region110 and the P-type well region 120 are separated from each other by theshallow trench isolation 102 at the surface of the semiconductorstructure, and are separated from each other with a distance below theshallow trench isolation 102.

Next, a gate dielectric 104 is then formed on the surface of thesemiconductor structure by the above conventional deposition process, asshown in FIG. 4. In an example, the gate dielectric 104 is athermally-grown oxide layer such as silicon oxide, with a thickness ofabout 10-15 nanometers.

Next, a gate conductor 105 is formed on the gate dielectric 104 by theabove conventional deposition process, as shown in FIG. 5. In anexample, the gate conductor 105 is a polysilicon layer, with a thicknessof about 200 nanometers. Next, a photoresist layer is formed on asurface of the semiconductor structure, and then patterned bylithography to be a photoresist mask PR3. Etching is performed throughthe photoresist mask PR3. The etching is performed from top to bottomthrough the openings in the photoresist mask to remove exposed portionsof the gate conductor 105 and the gate dielectric 104, as shown in FIG.6. Due to selectivity of the etchant, the etching stops at the surfaceof the N-type well region 110 and the P-type well region 120. In theetching, the pattern of the photoresist mask PR3 defines a shape of thegate stack. Then, the photoresist layer is removed by ashing ordissolution with a solvent.

Next, a third ion implantation is performed with the gate conductor 105and the shallow trench isolation 102 together as a hard mask, withoutusing an additional photoresist mask, to form a LDD region 111 in theN-type well region 110 near the surface and a LDD region 122 in theP-type well region 120 near the surface. An N-type dopant is used in theion implantation, as shown in FIG. 7. Thus, both the LDD region 111 andthe LDD region 122 are N-type doping regions.

Moreover, the N-type dopant is also implanted into the gate conductor105 of the P-type MOSFET and the N-type MOSFET in the ion implantation.

Next, a photoresist layer is formed on a surface of the semiconductorstructure, and then patterned by lithography to be a photoresist maskPR4. The photoresist mask PR4 blocks the active region of the N-typeMOSFET and exposes the active region of the P-type MOSFET. A fourth ionimplantation is performed by using the photoresist PR4. A dopant reachesthe N-type well region 110 through the openings in the photoresist maskPR4 in the implantation, as shown in FIG. 8. Then, the photoresist maskis removed by ashing or dissolution with a solvent.

A P-type dopant is used in the fourth ion implantation, which has adosage larger than that of the N-type dopant used in the third ionimplantation. Thus, the P-type dopant over dopes a region of the N-typeLDD region 111 to be a P-type LDD region 112.

Moreover, the N-type dopant is also implanted into only the gateconductor 105 of the P-type MOSFET.

Only one photoresist mask is used for the P-type MOSFET and the N-typeMOSFET in the third ion implantation and the fourth ion implantationwhen forming the above LDDs. Two opposite-types of LDD regions areformed by over doping even in a case that only one photoresist mask isused. Thus, the number of the photoresist masks is reduced. The failureof the CMOS structure due to mismatching of different masks is avoided.

Next, a nitride layer is then formed on the surface of the semiconductorstructure by the above conventional deposition process. In an example,the nitride layer is a silicon nitride layer with a thickness of about5-30 nanometers. Lateral portions of the nitride layer are removed byanisotropic etching, for example, reactive ion etching. Consequently,only vertical portions of the nitride layer remain at side walls of thegate conductor 105 to form gate spacers 106, as shown in FIG. 9.

Next, a photoresist layer is formed on a surface of the semiconductorstructure, and then patterned by lithography to be a mask PR5. Thephotoresist mask PR5 blocks the active region of the N-type MOSFET andexposes the active region of the P-type MOSFET. A fifth ion implantationis performed by using the photoresist mask PR5 and with the gateconductor 105, the gate spacers 106 and the shallow trench isolation 102together as a hard mask. A dopant reaches the N-type well region 110through the openings in the photoresist mask PR5 in the ion implantationto form P-type source/drain regions 115, as shown in FIG. 10. Moreover,the P-type dopant is also implanted into only the gate conductor 105 ofthe P-type MOSFET. A portion of the P-type LDD region 112 below the gatespacers 106 remains. Then, the photoresist mask is removed by ashing ordissolution with a solvent.

Next, a photoresist layer is formed on a surface of the semiconductorstructure, and then patterned by lithography to be photoresist mask PR6.The photoresist mask PR6 blocks the active region of the P-type MOSFETand exposes the active region of the N-type MOSFET. A sixth ionimplantation is performed by using the photoresist mask PR6 and with thegate conductor 105, the gate spacers 106 and the shallow trenchisolation 102 together as a hard mask. A dopant reaches the P-type wellregion 120 through the openings in the photoresist mask PR6 in the ionimplantation to form N-type source/drain regions 125, as shown in FIG.11. Moreover, the N-type dopant is also implanted into only the gateconductor 105 of the N-type MOSFET. A portion of the N-type LDD region122 below the gate spacers 106 remains. Then, the photoresist mask isremoved by ashing or dissolution with a solvent.

Preferably, spike anneal and/or laser anneal may be performed at thetemperature of about 1000-1100° C. to activate the dopants after thestep of forming the source/drain regions 125 for the N-type MOSFET andthe step of forming the source/drain regions 115 for the P-type MOSFET.

Preferably, a metal layer is formed on the surface of the semiconductorstructure by the above conventional deposition process, after the stepof forming the source/drain regions 125 for the N-type MOSFET and thestep of forming the source/drain regions 115 for the P-type MOSFET. Themetal layer is made of one from a group consisting of Ni, W, Ti, Co andalloys of any of Ni, W, Ti, Co with others. In an example, the metallayer is a Co layer formed by sputtering. In an example, thermal annealis then performed for about 1-10 seconds at the temperature of about300-500° C.

The thermal anneal causes silicidation of the metal layer at surfaces ofthe source/drain regions 125 of the N-type MOSFET and the source/drainregions 115 of the P-type MOSFET to form a metal silicide layer 107.Meanwhile, the silicidation also occurs at a surface of the gateconductor 105 to form the metal silicide layer 107. The metal silicidelayer 107 will reduce contact resistance of the source and drainregions. Remaining portions of the metal layer 111 are removed bywell-known dry etching or wet etching, as shown in FIG. 12.

After the steps described in connection with FIGS. 1 to 12, otherportions of the CMOS structure are then formed from the resultantsemiconductor structure, by subsequent steps of forming an interlayerdielectric layer, forming conductive plugs in the interlayer dielectriclayer, forming wirings and electrodes on the surface of the interlayerdielectric layer, and the like.

In the above embodiment, the active regions of the CMOS structure aredefined by shallow trench isolation. Alternatively, other isolationstructure may be used instead of the shallow trench isolation, forexample, a field oxide (FOX) or the like.

In the above embodiment, the N-type well region 110 and the P-type wellregion 120 are formed in the semiconductor substrate 101 respectively.However, only

P-type well region 120 can be formed, without the need for the N-typewell region 110, if the semiconductor substrate is N-type itself.Similarly, only N-type well region 110 can be formed, without the needfor the P-type well region 120, if the semiconductor substrate 101 isP-type itself.

In the above embodiment, the gate spacers 106 are formed after formingthe P-type LDD regions 112 and the N-type LDD regions 122.Alternatively, the gate spacers 106 may be formed before forming theP-type LDD regions 112 and the N-type LDD regions 122. Angledimplantation is then performed when forming the P-type LDD regions 112and the N-type LDD regions 122. The N-type dopant penetrates the gatespacers 106 and reaches the P-type well region 120 to form the N-typeLDD regions 122, and the P-type dopant penetrates the gate spacers 106and reaches the N-type well region 110 to form the P-type LDD regions112.

Also alternatively, the gate spacers may be formed after forming theN-type LDD regions 122 and before forming the P-type LDD regions 112.Angled implantation is then performed when forming the P-type LDDregions 112. The P-type dopant penetrates the gate spacers 106 andreaches the N-type well region to form the P-type LDD regions 112.

Instead of the step shown in FIG. 11, the source/drain regions 115 ofP-type MOSFET are formed immediately after forming the P-type LDDregions 112. A fourth ion implantation is performed by using thephotoresist mask PR4 and with the gate conductor 105, the gate spacers106 and the shallow trench isolation 102 together as a hard mask. Thedopant reaches the N-type well region 110 through the openings of thephotoresist mask PR4. A P-type dopant is used in the fourth ionimplantation, which has a dosage larger than that of the N-type dopantused in the third ion implantation. Thus, P-type source/drain regions115 are formed. The photoresist mask PR4 blocks the active region of theN-type MOSFET and exposes the active region of the P-type MOSFET. Then,the photoresist mask is removed by ashing or dissolution with a solvent.

The step shown in FIG. 10 then continues to form source/drain regions125 of N-type MOSFET. A photoresist mask PR5 is used in this step, whichblocks the active region of the P-type MOSFET and exposes the activeregion of the N-type MOSFET. A fifth ion implantation is performed byusing the photoresist mask PR5 and with the gate conductor 105, the gatespacers 106 and the shallow trench isolation 102 together as a hardmask. A dopant reaches the P-type well region 120 through the openingsin the photoresist mask PR5 in the ion implantation to form N-typesource/drain regions 125. Then, the photoresist mask is removed byashing or dissolution with a solvent.

In this embodiment, one photoresist mask is used for forming both theP-type LDD regions and the P-type source/drain regions. The photoresistmask PR6 shown in FIG. 11 can be omitted, which further reduces thenumber of the photoresist mask and the number of the process steps.

It should also be understood that the relational terms such as “first”,“second”, and the like are used in the context merely for distinguishingone element or operation form the other element or operation, instead ofmeaning or implying any real relationship or order of these elements oroperations. Moreover, the terms “comprise”, “comprising” and the likeare used to refer to comprise in nonexclusive sense, so that anyprocess, approach, article or apparatus relevant to an element, iffollows the terms, means that not only said element listed here, butalso those elements not listed explicitly, or those elements inherentlyincluded by the process, approach, article or apparatus relevant to saidelement. If there is no explicit limitation, the wording “comprise a/an. . . ” does not exclude the fact that other elements can also beincluded together with the process, approach, article or apparatusrelevant to the element.

Although various embodiments of the present invention are describedabove, these embodiments neither present all details, nor imply that thepresent invention is limited to these embodiments. Obviously, manymodifications and changes may be made in light of the teaching of theabove embodiments. These embodiments are presented and some details aredescribed herein only for explaining the principle of the invention andits actual use, so that one skilled person can practice the presentinvention and introduce some modifications in light of the invention.The invention is intended to cover alternatives, modifications andequivalents that may be included within the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. A method for manufacturing a CMOS structure,comprising: forming a first gate stack on a semiconductor substrate in afirst region; forming a second gate stack on said semiconductorsubstrate in a second region; implanting a dopant of a first type withsaid first gate stack and said second gate stack as a hard mask, to forma lightly-doped drain region of said first type; and implanting a dopantof a second type by using a first mask and with said second gate stackas a hard mask, to form a lightly-doped drain region of said secondtype, wherein said first mask blocks said first region and exposes saidsecond region, wherein when said lightly-doped drain region of saidsecond type is formed, said dopant of said second type over dopes apredetermined region of said lightly-doped drain region of said firsttype.
 2. The method according to claim 1, wherein each of said firstgate stack and said second gate stack comprises a gate conductor and agate dielectric, and said gate dielectric is disposed between said gateconductor and said semiconductor substrate.
 3. The method according toclaim 2, wherein said gate conductor is made of polysilicon.
 4. Themethod according to claim 3, after said steps of forming said first gatestack and forming said second gate stack, further comprising doping saidgate conductor of at least one of said first gate stack and said secondgate stack to adjust work function.
 5. The method according to claim 1,before said step of forming said first gate stack, further comprising atleast one of: forming a first well region of said second type byimplanting a dopant of said second type in said first region of saidsemiconductor substrate; and forming a second well region of said firsttype by implanting said dopant of said first type in said second regionof said semiconductor substrate.
 6. The method according to claim 5,wherein at least one of said first well region and said second wellregion has a doping concentration which is controlled in view of athreshold voltage.
 7. The method according to claim 1, before said stepof forming said first gate stack, further comprising: forming shallowtrench isolation in said semiconductor substrate for defining said firstregion for MOSFETs of said first type and said second region for MOSFETsof said second type.
 8. The method according to claim 1, after saidsteps of forming said first gate stack and forming said second gatestack, and before said steps of forming said lightly-doped drain regionof said first type and forming said lightly-doped drain region of saidsecond type, further comprising forming gate spacers on side walls ofsaid first gate stack and said second gate stack.
 9. The methodaccording to claim 1, after said steps of forming said lightly-dopeddrain region of said first type and forming said lightly-doped drainregion of said second type, further comprising forming gate spacers onside walls of said first gate stack and said second gate stack.
 10. Themethod according to claim 1, after said steps of forming said first gatestack and forming said second gate stack, and after said step of formingsaid lightly-doped drain region of said first type, and before said stepof forming said lightly-doped drain region of said second type, furthercomprising forming gate spacers on side walls of said first gate stackand said second gate stack.
 11. The method according to claim 9, furthercomprising: implanting a dopant of said first type by using a secondmask and with said first gate stack and said gate spacers as a hardmask, to form source/drain regions of said first type, wherein saidsecond mask blocks said second region and exposes said first region; andimplanting a dopant of said second type by using a third mask and withsaid second gate stack and said gate spacers as a hard mask, to formsource/drain regions of said second type, wherein said third mask blockssaid first region and exposes said second region.
 12. The methodaccording to claim 10, further comprising: implanting a dopant of saidsecond type by using said first mask and with said second gate stack andsaid gate spacers as a hard mask, to form said lightly-doped drainregion of said second type and source/drain regions of said second type,wherein said first mask blocks said first region and exposes said secondregion, and implanting a dopant of said first type by using a secondmask and with said first gate stack and said gate spacers as a hardmask, to form source/drain regions of said first type, wherein saidsecond mask blocks said second region and exposes said first region. 13.The method according to claim 12, further comprising implanting a dopantof said second type by angled ion implantation through said gate spacersto form said lightly-doped drain region of said second type.
 14. Themethod according to claim 1, after said steps of forming saidsource/drain regions of said first type and forming said source/drainregions of said second type, further comprising: performing silicidationto form a metal silicide layer on said source/drain regions of saidfirst type, on said source/drain regions of said second type, and onsaid gate stack.
 15. The method according to claim 2, wherein said gateconductor of said first gate stack contains a dopant of said first type,and said gate conductor of said second gate stack contains a dopant ofsaid first type and a dopant of said second type.